This invention relates to flash-memory drives/readers, and more particularly to parallel bus architectures to improve transfer speed.
Flash memory is widely used as a storage medium for a variety of applications. Flash memory uses electrically-erasable programmable read-only memory (EEPROM) as the non-volatile storage. For example, flash-memory cards can store digital pictures and video from a digital camera and transfer these pictures to a personal computer (PC). The flash-memory card is removed from the digital camera and inserted into a flash-memory reader attached to (or part of) the PC to transfer the pictures. Personal digital assistant (PDA's), music players, and other devices may also use flash-memory cards in a similar way.
A flash-card reader may be a stand-alone device that attaches to the PC using a Universal-Serial-Bus (USB), IEEE 1394, Integrated Device Electronics (IDE), serial AT-attachment (SATA), or other interface. See for example “FlashToaster for Reading Several Types of Flash-Memory Cards With or Without a PC”, U.S. Pat. No. 6,483,638, and its children.
USB is a popular interface. Data transfer rates up to 480 Mbps are supported. Unfortunately, flash-memory readers often operate woefully below the ideal transfer rate. For example, current readers may transfer data at a rate of only 7 MB/sec (56 Mbps). The slower transfer rate is undesirable, not just from a speed viewpoint, but because the slower speed can occupy more of the PC's resources for a longer time, reducing the PC's perceived performance. External flash drives that contain permanent flash memory rather than having slots for removable flash-memory cards may also connect to a PC through the USB interface.
FIG. 1 shows a prior-art flash drive. Flash-memory controller 20 reads or writes flash memory 8 that is a permanent or removable part of flash drive controller device 61. CPU 10 executes routines stored in ROM 12 that include routines to send commands to flash-memory controller 20 to read and write the flash memory. CPU 10 also controls serial engine 22, which transfers data serially over USB link 18.
CPU 10 may use scratch-pad RAM 14 to store parameters, execution states, or small amounts of data being reformatted during a transfer, but large amounts of the flash data being transferred is not normally stored in scratch-pad RAM 14. Data is normally transferred word-by-word directly from flash-memory controller 20 to CPU 10 and then to serial engine 22 without storage in scratch-pad RAM 14. New data words over-write any pervious data words, allowing scratch-pad RAM 14 to have a small capacity.
Data transfer rates are limited by bus 16. Bus 16 is a CPU-controlled bus. Master port 15 on CPU 10 acts as a bus master, controlling data transfer to and from one of slave ports 11, 17, 21, 23 on ROM 12, scratch-pad RAM 14, flash-memory controller 20, and serial engine 22, respectively.
FIG. 2 shows a prior-art flash-card reader. Flash-card controllers 24, 26 read or write flash memory on flash cards inserted into slots A, B of flash-card reader controller device 63. CPU 10 executes routines stored in ROM 12 that include routines to send commands to flash-card controllers 24, 26 to read and write the flash memory. CPU 10 also controls serial engine 22, which transfers data serially over USB link 18.
Data is normally transferred byte-by-byte directly from flash-card controllers 24, 26 to CPU 10 and then to serial engine 22 without storage in scratch-pad RAM 14. New data bytes over-write any pervious data bytes, allowing scratch-pad RAM 14 to have a small capacity. The width of bus 16 is often 8-bits (byte), but can be wider, and multiples of bus 16, such as 4, 8, or more burst transfers can occur.
Data transfer rates are limited by bus 16. Bus 16 is a CPU-controlled bus. Master port 15 on CPU 10 acts as a bus master, controlling data transfer to and from one of slave ports 11, 17, 23, 25, 27 on ROM 12, scratch-pad RAM 14, serial engine 22, and flash-card controllers 24, 26, respectively.
FIG. 3 shows a prior art PC with a USB interface. The flash drive/reader of FIGS. 1, 2 can be connected to USB link 128 of the PC in FIG. 3. CPU 104 executes programs for the user or operating system, using code in ROM 106 or in synchronous dynamic-random-access memory (SDRAM) 102. CPU 104 uses master port 105 to access SDRAM 102 through north bridge 108, which is an interface chip.
When transferring data such as a music file over USB link 128 to a flash card in an external reader, CPU 104 writes a data structure (from the music file, for example) in SDRAM 102. Then CPU 104 sends commands to USB host controller 122. CPU 104 uses its master port 105 to send the commands through north bridge 108 over Peripheral Component Interconnect (PCI) bus 120 to USB host controller 122. Master-slave port 123 on USB host controller 122 acts as a slave to receive these commands.
Once the commands are received by USB host controller 122, master-slave port 123 acts as a master of PCI bus 120. USB host controller 122 goes over PCI bus 120 and through north bridge 108 to read the data structure in SDRAM 102 that was earlier written by CPU 104. The data read from SDRAM 102 is then transmitted serially over USB link 128 by USB host controller 122. The serial engine on the external flash device can then accept the serial data and write the flash memory.
While such flash readers are useful and popular, the data transfer rates are limited by the bus architectures employed by the flash reader devices. More advanced bus structures are desirable to increase the data transfer rates. Higher transfer rates within a flash-memory drive or flash-card reader are desirable. Internal transfer rates that better match the USB transfer rates are desired.